Design for Testability (DFT) is an important requirement for today's complex application specific integrated circuit (ASIC) designs. DFT techniques allow one to perform high quality manufacturing tests after a chip has been synthesized, and to sort out good chips from bad ones. However, due to the ever increasing complexity of today's designs, the Automatic Test Equipment (ATE) tools required for testing are quite complex and expensive. As a result, manufacturing test costs have become a major part of the overall manufacturing cost of ASICs. Conventional testing approaches are unable to reduce this cost without sacrificing the test quality.
For example, the use of scan based Automatic Test Pattern Generation (ATPG) is a common DFT methodology that is widely used. Scan logic allows an internal sequential element of an ASIC, such as a flip-flop, to be controlled and observed during testing. The flip-flops are connected into several chains, called scan chains, which are usually accessed through test pins, as shown in FIG. 1. The test pins are normally shared with the functional chip pins. When testing is performed, the test vector data is applied through the chains to control the sequential state of the circuit to a desired state. After application of a test vector, the test response data is captured by the flip-flops. The response data is shifted out through the scan chains and is compared against the expected response to check if the chip is functioning correctly.
To achieve a high quality of the test, it is important to include most, if not all, of the flip-flops in the chip in the scan chains. The number of scan chains is usually limited to 16 or 32. The limit on the number of scan chains is bounded by the number of available input and output (I/O) pins that are able to access the chains, and by the number of scan-channels on an ATE used to drive the chains. Normally, one input and one output pin is required to access each chain. The chains are usually balanced as much as possible to minimize the length of the longest chain. The number of tester cycles required to shift data through a chain is determined by the length of the chain, i.e. by the number of flip-flops in the chain. Therefore, the length of the chains is limited to the number of pins, and the reduction in testing time is limited by the length of the chains. This conventional approach is inadequate for testing integrated circuits, because the required amount of testing time is inefficient for testing modern circuit designs.
Increasing the number of scan chains would reduce the maximum length of a scan chain, thus reducing the number of test cycles required to shift data through the chains. This directly impacts the test cost by reducing the test application time, but has no affect on the test data required to be stored in tester memory. However, conventional approaches fail to efficiently and cost-effectively do this.
For example, on-chip pseudo-random test generators based on Linear Feedback Shift Register (LFSR) or some derivation of it, are classified as Logic BIST techniques which are able to generate test vectors on chip. Hence, they can drive many more parallel scan chains. The data at the output of the chains is fed into an on-chip logic which computes a signature for the output response. This signature is finally serially shifted out to check the test response, or compared against the expected value stored on chip. For a given number of vectors, it would allow one to reduce the test application time, as well as test data required to be stored in tester memory. However, due to the randomness of the generated test patterns, the test quality is degraded. Such techniques are not able to achieve test results having a sufficient level of fault coverage for random logic designs.
Another method uses a hybrid approach of an LFSR based on-chip test generator, and an external scan based ATPG [1-7] tool. This uses the on-chip LFSR based test generator to drive several parallel scan chains. The ATPG tool is used to target test vectors that can be generated through the LFSR. Additional methods based on this hybrid approach add flexibility to the testing by several different techniques to allow generation of suitable test vectors, such as changing the state of the LFSR (also known as reseeding the LFSR), reconfiguring the LFSR by controlling the feedback taps on the LFSR, or by adding a phase-shifter at the output of the LFSR to change certain outputs of the LFSR as desired.
However, the hybrid techniques are inefficient, because designing the on-chip test generator, and modifying conventional ATPG tools to derive necessary seeds and/or feedback taps, are both expensive processes.